Fix the build on gcc-3.4.x (ia64 files)

Signed-off-by: Arun Sharma <arun.sharma@intel.com>

diff --git a/xen/arch/ia64/vcpu.c b/xen/arch/ia64/vcpu.c
index 49fef157c7ead985814aaf3ef5a58952888b5612..ed22389ab5e5eb8675226c5f1349d0e1b72ed117 100644 (file)
--- a/xen/arch/ia64/vcpu.c
+++ b/xen/arch/ia64/vcpu.c
@@ -392,6 +392,21 @@ IA64FAULT vcpu_get_ifa(VCPU *vcpu, UINT64 *pval)
        return (IA64_NO_FAULT);
 }
 
+unsigned long vcpu_get_rr_ps(VCPU *vcpu,UINT64 vadr)
+{
+       ia64_rr rr;
+
+       rr.rrval = PSCB(vcpu,rrs)[vadr>>61];
+       return(rr.ps);
+}
+
+unsigned long vcpu_get_rr_rid(VCPU *vcpu,UINT64 vadr)
+{
+       ia64_rr rr;
+
+       rr.rrval = PSCB(vcpu,rrs)[vadr>>61];
+       return(rr.rid);
+}
 
 unsigned long vcpu_get_itir_on_fault(VCPU *vcpu, UINT64 ifa)
 {
@@ -884,6 +899,15 @@ IA64FAULT vcpu_set_lrr1(VCPU *vcpu, UINT64 val)
        return (IA64_NO_FAULT);
 }
 
+// parameter is a time interval specified in cycles
+void vcpu_enable_timer(VCPU *vcpu,UINT64 cycles)
+{
+    PSCBX(vcpu,xen_timer_interval) = cycles;
+    vcpu_set_next_timer(vcpu);
+    printf("vcpu_enable_timer(%d): interval set to %d cycles\n",
+             PSCBX(vcpu,xen_timer_interval));
+    __set_bit(PSCB(vcpu,itv), PSCB(vcpu,delivery_mask));
+}
 
 IA64FAULT vcpu_set_itv(VCPU *vcpu, UINT64 val)
 {
@@ -1012,16 +1036,6 @@ void vcpu_set_next_timer(VCPU *vcpu)
        }
 }
 
-// parameter is a time interval specified in cycles
-void vcpu_enable_timer(VCPU *vcpu,UINT64 cycles)
-{
-    PSCBX(vcpu,xen_timer_interval) = cycles;
-    vcpu_set_next_timer(vcpu);
-    printf("vcpu_enable_timer(%d): interval set to %d cycles\n",
-             PSCBX(vcpu,xen_timer_interval));
-    __set_bit(PSCB(vcpu,itv), PSCB(vcpu,delivery_mask));
-}
-
 IA64FAULT vcpu_set_itm(VCPU *vcpu, UINT64 val)
 {
        UINT now = ia64_get_itc();
@@ -1219,7 +1233,6 @@ IA64FAULT vcpu_cover(VCPU *vcpu)
 
 IA64FAULT vcpu_thash(VCPU *vcpu, UINT64 vadr, UINT64 *pval)
 {
-       extern unsigned long vcpu_get_rr_ps(VCPU *vcpu,UINT64 vadr);
        UINT64 pta = PSCB(vcpu,pta);
        UINT64 pta_sz = (pta & IA64_PTA_SZ(0x3f)) >> IA64_PTA_SZ_BIT;
        UINT64 pta_base = pta & ~((1UL << IA64_PTA_BASE_BIT)-1);
@@ -1521,28 +1534,8 @@ unsigned long vcpu_get_rr_ve(VCPU *vcpu,UINT64 vadr)
        return(rr.ve);
 }
 
-
-unsigned long vcpu_get_rr_ps(VCPU *vcpu,UINT64 vadr)
-{
-       ia64_rr rr;
-
-       rr.rrval = PSCB(vcpu,rrs)[vadr>>61];
-       return(rr.ps);
-}
-
-
-unsigned long vcpu_get_rr_rid(VCPU *vcpu,UINT64 vadr)
-{
-       ia64_rr rr;
-
-       rr.rrval = PSCB(vcpu,rrs)[vadr>>61];
-       return(rr.rid);
-}
-
-
 IA64FAULT vcpu_set_rr(VCPU *vcpu, UINT64 reg, UINT64 val)
 {
-       extern void set_one_rr(UINT64, UINT64);
        PSCB(vcpu,rrs)[reg>>61] = val;
        // warning: set_one_rr() does it "live"
        set_one_rr(reg,val);

diff --git a/xen/include/asm-ia64/config.h b/xen/include/asm-ia64/config.h
index 71bf6ea2e3890605d6a67e285b93938c8d390161..a59e62e947fae495a2c7ccf1894f825e34c66c2b 100644 (file)
--- a/xen/include/asm-ia64/config.h
+++ b/xen/include/asm-ia64/config.h
@@ -230,6 +230,7 @@ struct screen_info { };
 
 #define FORCE_CRASH()  asm("break 0;;");
 
+void dummy_called(char *function);
 #define dummy()        dummy_called(__FUNCTION__)
 
 // these declarations got moved at some point, find a better place for them

diff --git a/xen/include/asm-ia64/regionreg.h b/xen/include/asm-ia64/regionreg.h
index aa590dfbf99b2e1e2298d2601fe33aba4dea4b55..c942c242bad15e10449dfc22f6f793cb48610517 100644 (file)
--- a/xen/include/asm-ia64/regionreg.h
+++ b/xen/include/asm-ia64/regionreg.h
@@ -39,4 +39,7 @@ typedef union ia64_rr {
 #define RR_RID(arg) (((arg) & 0x0000000000ffffff) << 8)
 #define RR_RID_MASK 0x00000000ffffff00L
 
+
+int set_one_rr(unsigned long rr, unsigned long val);
+
 #endif         /* !_REGIONREG_H_ */